/freebsd/sys/dev/bhnd/bhndb/ |
H A D | bhndb.c | 824b48ef Mon Sep 05 22:11:46 GMT 2016 Landon J. Fuller <landonf@FreeBSD.org> bhnd(4): Implement backplane interrupt handling.
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented.
Reviewed by: mizhka Approved by: adrian (mentor, implicit) 824b48ef Mon Sep 05 22:11:46 GMT 2016 Landon J. Fuller <landonf@FreeBSD.org> bhnd(4): Implement backplane interrupt handling.
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented.
Reviewed by: mizhka Approved by: adrian (mentor, implicit) 824b48ef Mon Sep 05 22:11:46 GMT 2016 Landon J. Fuller <landonf@FreeBSD.org> bhnd(4): Implement backplane interrupt handling.
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented.
Reviewed by: mizhka Approved by: adrian (mentor, implicit) 824b48ef Mon Sep 05 22:11:46 GMT 2016 Landon J. Fuller <landonf@FreeBSD.org> bhnd(4): Implement backplane interrupt handling.
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented.
Reviewed by: mizhka Approved by: adrian (mentor, implicit) 824b48ef Mon Sep 05 22:11:46 GMT 2016 Landon J. Fuller <landonf@FreeBSD.org> bhnd(4): Implement backplane interrupt handling.
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented.
Reviewed by: mizhka Approved by: adrian (mentor, implicit) 824b48ef Mon Sep 05 22:11:46 GMT 2016 Landon J. Fuller <landonf@FreeBSD.org> bhnd(4): Implement backplane interrupt handling.
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented.
Reviewed by: mizhka Approved by: adrian (mentor, implicit) 824b48ef Mon Sep 05 22:11:46 GMT 2016 Landon J. Fuller <landonf@FreeBSD.org> bhnd(4): Implement backplane interrupt handling.
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented.
Reviewed by: mizhka Approved by: adrian (mentor, implicit)
|
H A D | bhnd_bhndb.c | 824b48ef Mon Sep 05 22:11:46 GMT 2016 Landon J. Fuller <landonf@FreeBSD.org> bhnd(4): Implement backplane interrupt handling.
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented.
Reviewed by: mizhka Approved by: adrian (mentor, implicit) 824b48ef Mon Sep 05 22:11:46 GMT 2016 Landon J. Fuller <landonf@FreeBSD.org> bhnd(4): Implement backplane interrupt handling.
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented.
Reviewed by: mizhka Approved by: adrian (mentor, implicit) 824b48ef Mon Sep 05 22:11:46 GMT 2016 Landon J. Fuller <landonf@FreeBSD.org> bhnd(4): Implement backplane interrupt handling.
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented.
Reviewed by: mizhka Approved by: adrian (mentor, implicit) 824b48ef Mon Sep 05 22:11:46 GMT 2016 Landon J. Fuller <landonf@FreeBSD.org> bhnd(4): Implement backplane interrupt handling.
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented.
Reviewed by: mizhka Approved by: adrian (mentor, implicit) 824b48ef Mon Sep 05 22:11:46 GMT 2016 Landon J. Fuller <landonf@FreeBSD.org> bhnd(4): Implement backplane interrupt handling.
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented.
Reviewed by: mizhka Approved by: adrian (mentor, implicit) 824b48ef Mon Sep 05 22:11:46 GMT 2016 Landon J. Fuller <landonf@FreeBSD.org> bhnd(4): Implement backplane interrupt handling.
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented.
Reviewed by: mizhka Approved by: adrian (mentor, implicit) 824b48ef Mon Sep 05 22:11:46 GMT 2016 Landon J. Fuller <landonf@FreeBSD.org> bhnd(4): Implement backplane interrupt handling.
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented.
Reviewed by: mizhka Approved by: adrian (mentor, implicit)
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H A D | bhndb_pcivar.h | 824b48ef Mon Sep 05 22:11:46 GMT 2016 Landon J. Fuller <landonf@FreeBSD.org> bhnd(4): Implement backplane interrupt handling.
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented.
Reviewed by: mizhka Approved by: adrian (mentor, implicit) 824b48ef Mon Sep 05 22:11:46 GMT 2016 Landon J. Fuller <landonf@FreeBSD.org> bhnd(4): Implement backplane interrupt handling.
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented.
Reviewed by: mizhka Approved by: adrian (mentor, implicit) 824b48ef Mon Sep 05 22:11:46 GMT 2016 Landon J. Fuller <landonf@FreeBSD.org> bhnd(4): Implement backplane interrupt handling.
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented.
Reviewed by: mizhka Approved by: adrian (mentor, implicit) 824b48ef Mon Sep 05 22:11:46 GMT 2016 Landon J. Fuller <landonf@FreeBSD.org> bhnd(4): Implement backplane interrupt handling.
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented.
Reviewed by: mizhka Approved by: adrian (mentor, implicit) 824b48ef Mon Sep 05 22:11:46 GMT 2016 Landon J. Fuller <landonf@FreeBSD.org> bhnd(4): Implement backplane interrupt handling.
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented.
Reviewed by: mizhka Approved by: adrian (mentor, implicit) 824b48ef Mon Sep 05 22:11:46 GMT 2016 Landon J. Fuller <landonf@FreeBSD.org> bhnd(4): Implement backplane interrupt handling.
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented.
Reviewed by: mizhka Approved by: adrian (mentor, implicit) 824b48ef Mon Sep 05 22:11:46 GMT 2016 Landon J. Fuller <landonf@FreeBSD.org> bhnd(4): Implement backplane interrupt handling.
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented.
Reviewed by: mizhka Approved by: adrian (mentor, implicit)
|
H A D | bhndb_pci.c | 824b48ef Mon Sep 05 22:11:46 GMT 2016 Landon J. Fuller <landonf@FreeBSD.org> bhnd(4): Implement backplane interrupt handling.
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented.
Reviewed by: mizhka Approved by: adrian (mentor, implicit) 824b48ef Mon Sep 05 22:11:46 GMT 2016 Landon J. Fuller <landonf@FreeBSD.org> bhnd(4): Implement backplane interrupt handling.
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented.
Reviewed by: mizhka Approved by: adrian (mentor, implicit) 824b48ef Mon Sep 05 22:11:46 GMT 2016 Landon J. Fuller <landonf@FreeBSD.org> bhnd(4): Implement backplane interrupt handling.
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented.
Reviewed by: mizhka Approved by: adrian (mentor, implicit) 824b48ef Mon Sep 05 22:11:46 GMT 2016 Landon J. Fuller <landonf@FreeBSD.org> bhnd(4): Implement backplane interrupt handling.
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented.
Reviewed by: mizhka Approved by: adrian (mentor, implicit) 824b48ef Mon Sep 05 22:11:46 GMT 2016 Landon J. Fuller <landonf@FreeBSD.org> bhnd(4): Implement backplane interrupt handling.
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented.
Reviewed by: mizhka Approved by: adrian (mentor, implicit) 824b48ef Mon Sep 05 22:11:46 GMT 2016 Landon J. Fuller <landonf@FreeBSD.org> bhnd(4): Implement backplane interrupt handling.
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented.
Reviewed by: mizhka Approved by: adrian (mentor, implicit) 824b48ef Mon Sep 05 22:11:46 GMT 2016 Landon J. Fuller <landonf@FreeBSD.org> bhnd(4): Implement backplane interrupt handling.
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented.
Reviewed by: mizhka Approved by: adrian (mentor, implicit)
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/freebsd/sys/dev/bhnd/siba/ |
H A D | siba_bhndb.c | 824b48ef Mon Sep 05 22:11:46 GMT 2016 Landon J. Fuller <landonf@FreeBSD.org> bhnd(4): Implement backplane interrupt handling.
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented.
Reviewed by: mizhka Approved by: adrian (mentor, implicit) 824b48ef Mon Sep 05 22:11:46 GMT 2016 Landon J. Fuller <landonf@FreeBSD.org> bhnd(4): Implement backplane interrupt handling.
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented.
Reviewed by: mizhka Approved by: adrian (mentor, implicit) 824b48ef Mon Sep 05 22:11:46 GMT 2016 Landon J. Fuller <landonf@FreeBSD.org> bhnd(4): Implement backplane interrupt handling.
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented.
Reviewed by: mizhka Approved by: adrian (mentor, implicit) 824b48ef Mon Sep 05 22:11:46 GMT 2016 Landon J. Fuller <landonf@FreeBSD.org> bhnd(4): Implement backplane interrupt handling.
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented.
Reviewed by: mizhka Approved by: adrian (mentor, implicit) 824b48ef Mon Sep 05 22:11:46 GMT 2016 Landon J. Fuller <landonf@FreeBSD.org> bhnd(4): Implement backplane interrupt handling.
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented.
Reviewed by: mizhka Approved by: adrian (mentor, implicit) 824b48ef Mon Sep 05 22:11:46 GMT 2016 Landon J. Fuller <landonf@FreeBSD.org> bhnd(4): Implement backplane interrupt handling.
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented.
Reviewed by: mizhka Approved by: adrian (mentor, implicit) 824b48ef Mon Sep 05 22:11:46 GMT 2016 Landon J. Fuller <landonf@FreeBSD.org> bhnd(4): Implement backplane interrupt handling.
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented.
Reviewed by: mizhka Approved by: adrian (mentor, implicit)
|
H A D | siba.c | 824b48ef Mon Sep 05 22:11:46 GMT 2016 Landon J. Fuller <landonf@FreeBSD.org> bhnd(4): Implement backplane interrupt handling.
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented.
Reviewed by: mizhka Approved by: adrian (mentor, implicit) 824b48ef Mon Sep 05 22:11:46 GMT 2016 Landon J. Fuller <landonf@FreeBSD.org> bhnd(4): Implement backplane interrupt handling.
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented.
Reviewed by: mizhka Approved by: adrian (mentor, implicit) 824b48ef Mon Sep 05 22:11:46 GMT 2016 Landon J. Fuller <landonf@FreeBSD.org> bhnd(4): Implement backplane interrupt handling.
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented.
Reviewed by: mizhka Approved by: adrian (mentor, implicit) 824b48ef Mon Sep 05 22:11:46 GMT 2016 Landon J. Fuller <landonf@FreeBSD.org> bhnd(4): Implement backplane interrupt handling.
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented.
Reviewed by: mizhka Approved by: adrian (mentor, implicit) 824b48ef Mon Sep 05 22:11:46 GMT 2016 Landon J. Fuller <landonf@FreeBSD.org> bhnd(4): Implement backplane interrupt handling.
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented.
Reviewed by: mizhka Approved by: adrian (mentor, implicit) 824b48ef Mon Sep 05 22:11:46 GMT 2016 Landon J. Fuller <landonf@FreeBSD.org> bhnd(4): Implement backplane interrupt handling.
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented.
Reviewed by: mizhka Approved by: adrian (mentor, implicit) 824b48ef Mon Sep 05 22:11:46 GMT 2016 Landon J. Fuller <landonf@FreeBSD.org> bhnd(4): Implement backplane interrupt handling.
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented.
Reviewed by: mizhka Approved by: adrian (mentor, implicit)
|
H A D | sibareg.h | 824b48ef Mon Sep 05 22:11:46 GMT 2016 Landon J. Fuller <landonf@FreeBSD.org> bhnd(4): Implement backplane interrupt handling.
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented.
Reviewed by: mizhka Approved by: adrian (mentor, implicit) 824b48ef Mon Sep 05 22:11:46 GMT 2016 Landon J. Fuller <landonf@FreeBSD.org> bhnd(4): Implement backplane interrupt handling.
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented.
Reviewed by: mizhka Approved by: adrian (mentor, implicit) 824b48ef Mon Sep 05 22:11:46 GMT 2016 Landon J. Fuller <landonf@FreeBSD.org> bhnd(4): Implement backplane interrupt handling.
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented.
Reviewed by: mizhka Approved by: adrian (mentor, implicit) 824b48ef Mon Sep 05 22:11:46 GMT 2016 Landon J. Fuller <landonf@FreeBSD.org> bhnd(4): Implement backplane interrupt handling.
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented.
Reviewed by: mizhka Approved by: adrian (mentor, implicit) 824b48ef Mon Sep 05 22:11:46 GMT 2016 Landon J. Fuller <landonf@FreeBSD.org> bhnd(4): Implement backplane interrupt handling.
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented.
Reviewed by: mizhka Approved by: adrian (mentor, implicit) 824b48ef Mon Sep 05 22:11:46 GMT 2016 Landon J. Fuller <landonf@FreeBSD.org> bhnd(4): Implement backplane interrupt handling.
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented.
Reviewed by: mizhka Approved by: adrian (mentor, implicit) 824b48ef Mon Sep 05 22:11:46 GMT 2016 Landon J. Fuller <landonf@FreeBSD.org> bhnd(4): Implement backplane interrupt handling.
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented.
Reviewed by: mizhka Approved by: adrian (mentor, implicit)
|
H A D | sibavar.h | 824b48ef Mon Sep 05 22:11:46 GMT 2016 Landon J. Fuller <landonf@FreeBSD.org> bhnd(4): Implement backplane interrupt handling.
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented.
Reviewed by: mizhka Approved by: adrian (mentor, implicit) 824b48ef Mon Sep 05 22:11:46 GMT 2016 Landon J. Fuller <landonf@FreeBSD.org> bhnd(4): Implement backplane interrupt handling.
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented.
Reviewed by: mizhka Approved by: adrian (mentor, implicit) 824b48ef Mon Sep 05 22:11:46 GMT 2016 Landon J. Fuller <landonf@FreeBSD.org> bhnd(4): Implement backplane interrupt handling.
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented.
Reviewed by: mizhka Approved by: adrian (mentor, implicit) 824b48ef Mon Sep 05 22:11:46 GMT 2016 Landon J. Fuller <landonf@FreeBSD.org> bhnd(4): Implement backplane interrupt handling.
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented.
Reviewed by: mizhka Approved by: adrian (mentor, implicit) 824b48ef Mon Sep 05 22:11:46 GMT 2016 Landon J. Fuller <landonf@FreeBSD.org> bhnd(4): Implement backplane interrupt handling.
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented.
Reviewed by: mizhka Approved by: adrian (mentor, implicit) 824b48ef Mon Sep 05 22:11:46 GMT 2016 Landon J. Fuller <landonf@FreeBSD.org> bhnd(4): Implement backplane interrupt handling.
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented.
Reviewed by: mizhka Approved by: adrian (mentor, implicit) 824b48ef Mon Sep 05 22:11:46 GMT 2016 Landon J. Fuller <landonf@FreeBSD.org> bhnd(4): Implement backplane interrupt handling.
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented.
Reviewed by: mizhka Approved by: adrian (mentor, implicit)
|
/freebsd/sys/dev/bhnd/cores/pmu/ |
H A D | bhnd_pmu_subr.c | 824b48ef Mon Sep 05 22:11:46 GMT 2016 Landon J. Fuller <landonf@FreeBSD.org> bhnd(4): Implement backplane interrupt handling.
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented.
Reviewed by: mizhka Approved by: adrian (mentor, implicit) 824b48ef Mon Sep 05 22:11:46 GMT 2016 Landon J. Fuller <landonf@FreeBSD.org> bhnd(4): Implement backplane interrupt handling.
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented.
Reviewed by: mizhka Approved by: adrian (mentor, implicit) 824b48ef Mon Sep 05 22:11:46 GMT 2016 Landon J. Fuller <landonf@FreeBSD.org> bhnd(4): Implement backplane interrupt handling.
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented.
Reviewed by: mizhka Approved by: adrian (mentor, implicit) 824b48ef Mon Sep 05 22:11:46 GMT 2016 Landon J. Fuller <landonf@FreeBSD.org> bhnd(4): Implement backplane interrupt handling.
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented.
Reviewed by: mizhka Approved by: adrian (mentor, implicit) 824b48ef Mon Sep 05 22:11:46 GMT 2016 Landon J. Fuller <landonf@FreeBSD.org> bhnd(4): Implement backplane interrupt handling.
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented.
Reviewed by: mizhka Approved by: adrian (mentor, implicit) 824b48ef Mon Sep 05 22:11:46 GMT 2016 Landon J. Fuller <landonf@FreeBSD.org> bhnd(4): Implement backplane interrupt handling.
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented.
Reviewed by: mizhka Approved by: adrian (mentor, implicit) 824b48ef Mon Sep 05 22:11:46 GMT 2016 Landon J. Fuller <landonf@FreeBSD.org> bhnd(4): Implement backplane interrupt handling.
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented.
Reviewed by: mizhka Approved by: adrian (mentor, implicit)
|
/freebsd/sys/dev/bhnd/bcma/ |
H A D | bcma.c | 824b48ef Mon Sep 05 22:11:46 GMT 2016 Landon J. Fuller <landonf@FreeBSD.org> bhnd(4): Implement backplane interrupt handling.
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented.
Reviewed by: mizhka Approved by: adrian (mentor, implicit) 824b48ef Mon Sep 05 22:11:46 GMT 2016 Landon J. Fuller <landonf@FreeBSD.org> bhnd(4): Implement backplane interrupt handling.
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented.
Reviewed by: mizhka Approved by: adrian (mentor, implicit) 824b48ef Mon Sep 05 22:11:46 GMT 2016 Landon J. Fuller <landonf@FreeBSD.org> bhnd(4): Implement backplane interrupt handling.
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented.
Reviewed by: mizhka Approved by: adrian (mentor, implicit) 824b48ef Mon Sep 05 22:11:46 GMT 2016 Landon J. Fuller <landonf@FreeBSD.org> bhnd(4): Implement backplane interrupt handling.
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented.
Reviewed by: mizhka Approved by: adrian (mentor, implicit) 824b48ef Mon Sep 05 22:11:46 GMT 2016 Landon J. Fuller <landonf@FreeBSD.org> bhnd(4): Implement backplane interrupt handling.
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented.
Reviewed by: mizhka Approved by: adrian (mentor, implicit) 824b48ef Mon Sep 05 22:11:46 GMT 2016 Landon J. Fuller <landonf@FreeBSD.org> bhnd(4): Implement backplane interrupt handling.
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented.
Reviewed by: mizhka Approved by: adrian (mentor, implicit) 824b48ef Mon Sep 05 22:11:46 GMT 2016 Landon J. Fuller <landonf@FreeBSD.org> bhnd(4): Implement backplane interrupt handling.
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented.
Reviewed by: mizhka Approved by: adrian (mentor, implicit)
|
H A D | bcma_dmp.h | 824b48ef Mon Sep 05 22:11:46 GMT 2016 Landon J. Fuller <landonf@FreeBSD.org> bhnd(4): Implement backplane interrupt handling.
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented.
Reviewed by: mizhka Approved by: adrian (mentor, implicit) 824b48ef Mon Sep 05 22:11:46 GMT 2016 Landon J. Fuller <landonf@FreeBSD.org> bhnd(4): Implement backplane interrupt handling.
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented.
Reviewed by: mizhka Approved by: adrian (mentor, implicit) 824b48ef Mon Sep 05 22:11:46 GMT 2016 Landon J. Fuller <landonf@FreeBSD.org> bhnd(4): Implement backplane interrupt handling.
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented.
Reviewed by: mizhka Approved by: adrian (mentor, implicit) 824b48ef Mon Sep 05 22:11:46 GMT 2016 Landon J. Fuller <landonf@FreeBSD.org> bhnd(4): Implement backplane interrupt handling.
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented.
Reviewed by: mizhka Approved by: adrian (mentor, implicit) 824b48ef Mon Sep 05 22:11:46 GMT 2016 Landon J. Fuller <landonf@FreeBSD.org> bhnd(4): Implement backplane interrupt handling.
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented.
Reviewed by: mizhka Approved by: adrian (mentor, implicit) 824b48ef Mon Sep 05 22:11:46 GMT 2016 Landon J. Fuller <landonf@FreeBSD.org> bhnd(4): Implement backplane interrupt handling.
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented.
Reviewed by: mizhka Approved by: adrian (mentor, implicit) 824b48ef Mon Sep 05 22:11:46 GMT 2016 Landon J. Fuller <landonf@FreeBSD.org> bhnd(4): Implement backplane interrupt handling.
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented.
Reviewed by: mizhka Approved by: adrian (mentor, implicit)
|
H A D | bcmavar.h | 824b48ef Mon Sep 05 22:11:46 GMT 2016 Landon J. Fuller <landonf@FreeBSD.org> bhnd(4): Implement backplane interrupt handling.
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented.
Reviewed by: mizhka Approved by: adrian (mentor, implicit) 824b48ef Mon Sep 05 22:11:46 GMT 2016 Landon J. Fuller <landonf@FreeBSD.org> bhnd(4): Implement backplane interrupt handling.
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented.
Reviewed by: mizhka Approved by: adrian (mentor, implicit) 824b48ef Mon Sep 05 22:11:46 GMT 2016 Landon J. Fuller <landonf@FreeBSD.org> bhnd(4): Implement backplane interrupt handling.
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented.
Reviewed by: mizhka Approved by: adrian (mentor, implicit) 824b48ef Mon Sep 05 22:11:46 GMT 2016 Landon J. Fuller <landonf@FreeBSD.org> bhnd(4): Implement backplane interrupt handling.
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented.
Reviewed by: mizhka Approved by: adrian (mentor, implicit) 824b48ef Mon Sep 05 22:11:46 GMT 2016 Landon J. Fuller <landonf@FreeBSD.org> bhnd(4): Implement backplane interrupt handling.
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented.
Reviewed by: mizhka Approved by: adrian (mentor, implicit) 824b48ef Mon Sep 05 22:11:46 GMT 2016 Landon J. Fuller <landonf@FreeBSD.org> bhnd(4): Implement backplane interrupt handling.
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented.
Reviewed by: mizhka Approved by: adrian (mentor, implicit) 824b48ef Mon Sep 05 22:11:46 GMT 2016 Landon J. Fuller <landonf@FreeBSD.org> bhnd(4): Implement backplane interrupt handling.
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented.
Reviewed by: mizhka Approved by: adrian (mentor, implicit)
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/freebsd/sys/dev/bhnd/ |
H A D | bhnd_bus_if.m | 824b48ef Mon Sep 05 22:11:46 GMT 2016 Landon J. Fuller <landonf@FreeBSD.org> bhnd(4): Implement backplane interrupt handling.
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented.
Reviewed by: mizhka Approved by: adrian (mentor, implicit) 824b48ef Mon Sep 05 22:11:46 GMT 2016 Landon J. Fuller <landonf@FreeBSD.org> bhnd(4): Implement backplane interrupt handling.
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented.
Reviewed by: mizhka Approved by: adrian (mentor, implicit) 824b48ef Mon Sep 05 22:11:46 GMT 2016 Landon J. Fuller <landonf@FreeBSD.org> bhnd(4): Implement backplane interrupt handling.
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented.
Reviewed by: mizhka Approved by: adrian (mentor, implicit) 824b48ef Mon Sep 05 22:11:46 GMT 2016 Landon J. Fuller <landonf@FreeBSD.org> bhnd(4): Implement backplane interrupt handling.
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented.
Reviewed by: mizhka Approved by: adrian (mentor, implicit) 824b48ef Mon Sep 05 22:11:46 GMT 2016 Landon J. Fuller <landonf@FreeBSD.org> bhnd(4): Implement backplane interrupt handling.
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented.
Reviewed by: mizhka Approved by: adrian (mentor, implicit) 824b48ef Mon Sep 05 22:11:46 GMT 2016 Landon J. Fuller <landonf@FreeBSD.org> bhnd(4): Implement backplane interrupt handling.
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented.
Reviewed by: mizhka Approved by: adrian (mentor, implicit) 824b48ef Mon Sep 05 22:11:46 GMT 2016 Landon J. Fuller <landonf@FreeBSD.org> bhnd(4): Implement backplane interrupt handling.
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented.
Reviewed by: mizhka Approved by: adrian (mentor, implicit)
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H A D | bhnd.c | 824b48ef Mon Sep 05 22:11:46 GMT 2016 Landon J. Fuller <landonf@FreeBSD.org> bhnd(4): Implement backplane interrupt handling.
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented.
Reviewed by: mizhka Approved by: adrian (mentor, implicit) 824b48ef Mon Sep 05 22:11:46 GMT 2016 Landon J. Fuller <landonf@FreeBSD.org> bhnd(4): Implement backplane interrupt handling.
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented.
Reviewed by: mizhka Approved by: adrian (mentor, implicit) 824b48ef Mon Sep 05 22:11:46 GMT 2016 Landon J. Fuller <landonf@FreeBSD.org> bhnd(4): Implement backplane interrupt handling.
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented.
Reviewed by: mizhka Approved by: adrian (mentor, implicit) 824b48ef Mon Sep 05 22:11:46 GMT 2016 Landon J. Fuller <landonf@FreeBSD.org> bhnd(4): Implement backplane interrupt handling.
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented.
Reviewed by: mizhka Approved by: adrian (mentor, implicit) 824b48ef Mon Sep 05 22:11:46 GMT 2016 Landon J. Fuller <landonf@FreeBSD.org> bhnd(4): Implement backplane interrupt handling.
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented.
Reviewed by: mizhka Approved by: adrian (mentor, implicit) 824b48ef Mon Sep 05 22:11:46 GMT 2016 Landon J. Fuller <landonf@FreeBSD.org> bhnd(4): Implement backplane interrupt handling.
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented.
Reviewed by: mizhka Approved by: adrian (mentor, implicit) 824b48ef Mon Sep 05 22:11:46 GMT 2016 Landon J. Fuller <landonf@FreeBSD.org> bhnd(4): Implement backplane interrupt handling.
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented.
Reviewed by: mizhka Approved by: adrian (mentor, implicit)
|
H A D | bhnd.h | 824b48ef Mon Sep 05 22:11:46 GMT 2016 Landon J. Fuller <landonf@FreeBSD.org> bhnd(4): Implement backplane interrupt handling.
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented.
Reviewed by: mizhka Approved by: adrian (mentor, implicit) 824b48ef Mon Sep 05 22:11:46 GMT 2016 Landon J. Fuller <landonf@FreeBSD.org> bhnd(4): Implement backplane interrupt handling.
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented.
Reviewed by: mizhka Approved by: adrian (mentor, implicit) 824b48ef Mon Sep 05 22:11:46 GMT 2016 Landon J. Fuller <landonf@FreeBSD.org> bhnd(4): Implement backplane interrupt handling.
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented.
Reviewed by: mizhka Approved by: adrian (mentor, implicit) 824b48ef Mon Sep 05 22:11:46 GMT 2016 Landon J. Fuller <landonf@FreeBSD.org> bhnd(4): Implement backplane interrupt handling.
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented.
Reviewed by: mizhka Approved by: adrian (mentor, implicit) 824b48ef Mon Sep 05 22:11:46 GMT 2016 Landon J. Fuller <landonf@FreeBSD.org> bhnd(4): Implement backplane interrupt handling.
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented.
Reviewed by: mizhka Approved by: adrian (mentor, implicit) 824b48ef Mon Sep 05 22:11:46 GMT 2016 Landon J. Fuller <landonf@FreeBSD.org> bhnd(4): Implement backplane interrupt handling.
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented.
Reviewed by: mizhka Approved by: adrian (mentor, implicit) 824b48ef Mon Sep 05 22:11:46 GMT 2016 Landon J. Fuller <landonf@FreeBSD.org> bhnd(4): Implement backplane interrupt handling.
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation.
On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores.
On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented.
Reviewed by: mizhka Approved by: adrian (mentor, implicit)
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